Field effect transistors (FETs) can be semiconductor devices fabricated on a bulk semiconductor substrate or on a silicon-on-insulator (SOI) substrate. FET devices generally consist of a source, a drain, a gate, and a channel between the source and drain. The gate is separated from the channel by a thin insulating layer, typically of silicon oxide, called the field or gate oxide. A voltage drop generated by the gate across the oxide layer induces a conducting channel between the source and drain thereby controlling the current flow between the source and the drain. Current integrated circuit designs use complementary metal-oxide-semiconductor (CMOS) technology that use complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.
The integrated circuit industry is continually reducing the size of the devices, increasing the number of circuits that can be produced on a given substrate or chip. It is also desirable to increase the performance of these circuits, increase the speed, and reduce the power consumption.
A three dimensional chip fabrication approach, such as a finFET, has been developed for semiconductor devices. A finFET is a non-planar FET versus the more standard planar FET. The “fin” is a narrow, vertical silicon base channel between the source and the drain. The fin is covered by the thin gate oxide and surrounded on two or three sides by an overlying gate structure. The multiple surfaces of the gate allow for more effective suppression of “off-state” leakage current. The multiple surfaces of the gate also allow enhanced current in the “on” state, also known as drive current. These advantages translate to lower power consumption and enhanced device performance.
Process challenges exist as the dimensions of the planar and non-planar devices decrease, some now falling below 20 nm. Capacitance is the ability to store an electric charge, and parasitic capacitance is common inside electronic devices whenever two conductors are parallel to each other. As the dimensions of the devices decrease, the spacing between the various circuit elements also decreases, leading to increased parasitic capacitance. Parasitic capacitance is the unwanted capacitance that exists between the parts of an electronic component or circuit simply because of their proximity to each other. The increased parasitic capacitance can have detrimental effects on the circuit performance, limiting the frequency response of the device.